The present invention relates generally to an improvement in semiconductor fabrication processes, and more particularly, to an improvement in processes to form complementary metal oxide semiconductor (CMOS) transistors, particularly to CMOS devices having lightly doped drains, and source/drain active regions.
Conventional CMOS processes form MOS transistors by employing a number of steps, many of which require application of a specialized mask, introduction of dopants with the mask, and removal of the mask followed by another mask. The number of process steps required, and the number of masks required, are measures of a complexity of the semiconductor fabrication process. Decreasing both the number of masks, and the number of steps required to produce the semiconductor device, are desirable goals.
CMOS devices typically include two adjacent transistors, an n-channel transistor and a p-channel transistor, as well known. A conventional process will typically have separate masking steps for lightly doped drain implants in the n-channel transistors, and in the p-channel transistors, as well as separate source/drain implant masks for n conductivity type dopants and p-conductivity type dopants.
Conventional processes may also use p-well masks, and n-well masks to define the channel regions in the CMOS device. These masks, when used, are applied early in the processing sequence, typically before formation of gate structures.
A CMOS fabrication process that can simplify the formation of transistors without degrading their performance is desirable. Especially desirable would be an improved CMOS fabrication process that not only simplifies existing processes, but also that allows implementation of features that enhance performance over transistors made with conventional processes.